1. Field of the Invention
The present invention relates to signal magnitude detectors in general and more particularly to signal magnitude detectors implemented in data acquisition signal systems using CMOS technology.
2. Prior Art
The use of circuit arrangements for recovering information from a communications channel is well known in the prior art. Even though the prior art circuit arrangements may differ in implementation details, the general approach is that the circuits set a threshold level for an incoming signal. If the incoming signal exceeds the threshold level, it is characterized as data. Incoming signals that do not exceed the threshold level are characterized as noise.
Prior art circuit arrangements which vary from the above design technique include the following patents: U.S. Pat. No. 3,760,282. The subject patent describes a circuit arrangement which logically combines output signals from one or more threshold detectors and one or more peak detectors to form an output signal representative of received data.
U.S. Pat. No. 4,219,152 describes a circuit arrangement for reading bar codes imprinted on UPC labels. The circuit arrangement comprises of a comparative amplifier which compares an analog signal representative of a bar code pattern and an adjusted threshold signal generated from a slope detector, a negative peak detector and a positive peak detector.
U.S. Pat. No. 3,893,180 uses negative and positive threshold detectors for measuring the strength of prerecorded servo tracks on a disc and uses the information to position a magnetic head relative to a track on the disc.
U.S. Pat. No. 4,030,040 describes a circuit arrangement which selects the most desired signal from similar signals provided by two or more radio receivers. The circuit arrangement includes a log amplifier connected in series with an absolute value filter. A pair of peak and valley detectors are connected in parallel. The absolute valley filter is connected to the inputs of the detectors and the output of the detectors is connected to an operational amplifier arranged in a standard subtract configuration.
Even though the above circuits work well for their respective purposes, they have certain shortcomings which make them unsuitable for use in certain environments or be implemented with certain technologies. Among the shortcomings is the fact that the above circuit arrangements are implemented in bipolar technology. This technology is well known and is best suited for fabricating either digital or analog circuit modules. However, the increasing demand for VLSI circuits makes it necessary to integrate both analog and digital circuits on the same chip. A review of prior art literature indicates that CMOS is the technology of choices for fabricating modules which include both digital and analog circuits.
Even though CMOS is the preferred technology for fabricating mixed modules (i.e., a module which includes both digital and analog circuitries), there are certain problems which must be recognized and overcome before the CMOS process can be used efficiently. Because the above-described prior art fails to recognize these problems and have implemented the respective circuits in bipolar technology suggests that the prior art circuits are not intended to be used in VLSI chips with mixed circuits. In addition, the type of components used in the above prior art circuits further suggest that fabricating them with the CMOS process would not be economical.
One of the problems which must be overcome in using CMOS technology to fabricate analog and digital circuits on a common substrate is that only a single power supply level, usually +5 v, is available. The digital circuits are either "ON" or "OFF" and as a result requires only a single voltage supply. However, analog circuits must be operated in their linear region where circuit nodes are biased at voltage levels, in this case, between the power supply level and common ground. Therefore, an a.c. ground somewhere between the power supply level and common ground must be provided. Optimally, this a.c. ground is Vdd/2 (Vdd being the single voltage supply). However, since Vdd has a tolerance associated with its value, this a.c. ground is no longer a stable reference. Even so, it is still a common reference if it can be accurately reproduced throughout the system. Hence, the first problem was providing such a reference that is also insensitive to CMOS process variations.
Another problem occurs when the mixed module has to recover signals within the millivolt range. Such small signals are not uncommon in communications channels such as LANs (Local Area Networks), etc. Incidentally, such small signals cannot be recovered by the above described prior art circuits because they are well below the threshold levels which would activate their operation.
The problem which these small signals create for the CMOS implementation is that inaccuracies caused by mismatched devices can be a relatively high percentage of the signal magnitude to be recovered. For example, published data has shown that thresholds mismatched between source coupled pairs of FET devices alone are in the order of tens of millivolts. Source coupled paired FET devices are required in differential amplifiers, operational amplifiers, comparators, etc. In addition, published reports also show that some CMOS processes may have a .+-.15 mv margin. If the total signal magnitude of the signal to be recovered is 50 mv, then a mismatch of .+-.15 mv is a significant part of the total signal magnitude (approximately 30%).
Still another CMOS technology problem concerns common mode shifting. Common mode shifting is the variation in the common or d.c. component of a time varying signal. Such variations can be caused by variations in a.c. ground (i.e., variations in power supply), component mismatch, or a signal that is not always symmetrical around a.c. ground. All of the above are possible occurrences in the described system. Special techniques were therefore developed to quantify signals that experience common mode shifting.
A common system problem which affects not only the CMOS designed system but also the prior art bipolar designed system is the inability to track or recover a signal having variable magnitude.
Peak detectors are often used to quantify the voltage magnitude of a received signal. Peak detectors are linear circuits that continuously store the maximum or the minimum peak voltage level of a time varying signal. If the time varying signal is very small in magnitude, then the design of the peak detector can be optimized for low signal levels. However, there are systems that produce predominantly low signal levels with high level components. For example, the data signal received by adapters from some types of LANs (such as the LAN described by the 802.2 and 802.5 IEEE Standard Committee) can be very small in magnitude depending on the system characteristics. It is possible that the protocol data, which appears before and after the main data, can consist of information which is transmitted at one-half the frequency of the main data. For example, delimiter bits are transmitted at one-half the frequency of the main data. Since data transmitted at lower frequencies has more energy than data transmitted at higher frequencies within the same system, the former would not be attenuated as much as the latter. Hence, signal components very large in magnitude can be present in the midst of the low signal levels at the receiving end of the described system. If a peak detector is optimally designed for low signal levels, then the presence of such high level components can effectively mask the signal of interest. In other words, given the described system, a conventional peak detector would store the voltage level provided by the high level components regardless of the low signal levels.
This last problem concerns that of converting a differentially (double ended) quantified value to a single ended one. The peak detected signal magnitude in the disclosed subsystem is a differential value between two voltage levels. This presents a problem because this differential value must be compared to a single ended reference value. Therefore, a technique for converting the peak detected signal magnitude from double ended to single ended is required.